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84 Floating Point Adders: (ema3,add3) is an a+b+c adder and (ema2,add2) is an a+b adder. Ema's are blocks to normalize the exponents and shift the mantissas as required, add's are blocks that make the mantissa addition and normalize the result again into a 32 bit IEEE float format jguarin2002 4900d 23h /
83 Only to have it as an example of what to do to sign a mantissa jguarin2002 4900d 23h /
82 FPBRANCH releaseeeesvn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd jguarin2002 4903d 18h /
81 Almost There jguarin2002 4907d 16h /
80 not a revision jguarin2002 4908d 08h /
79 I can't use a 20 bits mantissa.... eliminating optimization jguarin2002 4912d 02h /
78 Metamorphosis jguarin2002 4919d 15h /
77 Now support for addition and substraction of A(7,10) component vectors jguarin2002 4920d 04h /
76 Upgrade para obtener una mantissa de 20 bits jguarin2002 4922d 02h /
75 Optimization done on matissa lenght for x**-1 and x**0.5, getting a longer mantissa of 20 bits instead one of 18 bits jguarin2002 4923d 21h /
74 On the rush, correct chip floor planning problem jguarin2002 4928d 15h /
73 Almost Ready Division and Square Root jguarin2002 4929d 20h /
72 Minor changes, is more a matter of format rather than anything... jguarin2002 4930d 08h /
71 RLshifterAlfa jguarin2002 4933d 01h /
70 RLshifterbeta++ jguarin2002 4933d 02h /
69 RLshifterbeta jguarin2002 4933d 04h /
68 On the rush cant explain what I did, but sure its about sqrtdiv jguarin2002 4933d 15h /
67 On the rush cant explain what I did, but sure its about sqrtdiv jguarin2002 4935d 17h /
66 tb.vhd moved to testbench directory jguarin2002 4937d 05h /
65 move memmaker to utils directory jguarin2002 4937d 05h /

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