URL https://opencores.org/ocsvn/rio/rio/trunk

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[/] - Rev 21

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Rev	Log message	Author	Age	Path
21	Branching of a single symbol version of the new RioSerial.	magro732	3980d 11h	/
20	Adding software C-stack and matching VHDL modules.	magro732	4045d 13h	/
19	Removing synthesis warnings.	magro732	4070d 13h	/
18	Making RioSerial entity the same as before+minor fixes.	magro732	4071d 11h	/
17	Removing latch and improving timing.	magro732	4072d 12h	/
16	Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing.	magro732	4072d 13h	/
15	All testcases are ok. Still needs some tweeks though.	magro732	4076d 13h	/
14	Most issues solved, testbench issues remains.	magro732	4079d 12h	/
13	Timeouts are working.	magro732	4082d 13h	/
12	Backup of recent work, debugging new RioSerial.	magro732	4093d 12h	/
11	Receiver ready, transmitter is compiling.	magro732	4093d 13h	/
10	Branch to develop support for parallel symbols.	magro732	4093d 13h	/
9	Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)	azdem	4135d 00h	/
8	Adding signal descriptions in comments.	magro732	4178d 14h	/
7	Adding missing generic parameters to RioPacketBuffer.	magro732	4265d 17h	/
6	Adding RioWbBridge. Sorry, no testbench for this one.	magro732	4265d 20h	/
5	Uploading primitive documentation.	magro732	4272d 12h	/
4	Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification.	magro732	4295d 01h	/
3	Adding RioPacketBuffer and testbench.	magro732	4295d 17h	/
2	Adding RioSwitch and testbench.	magro732	4295d 19h	/

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[/] - Rev 21

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