URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 117

Rev	Log message	Author	Age	Path
117	Uart im mem_stage	trinklhar	6403d 08h	/
116	writes to uart when write to reg 0	trinklhar	6404d 14h	/
115	* empty log message *	trinklhar	6405d 04h	/
114	Uart 0.3	trinklhar	6406d 09h	/
113	Uart reset funkt	trinklhar	6406d 10h	/
112	Uart drin aber signale nicht eingebunden	trinklhar	6406d 11h	/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6409d 03h	/
110	- Added missing file to CVS.	cwalter	6409d 10h	/
109	- Assembler code for ST produced wrong instruction format.	cwalter	6410d 01h	/
108	no message	cwalter	6410d 01h	/
107	- Added new example for memory testing.	cwalter	6410d 02h	/
106	- ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT.	cwalter	6410d 02h	/
105	- OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT.	cwalter	6410d 02h	/
104	- Added missing signal dmem_data_in.	cwalter	6410d 02h	/
103	- Added simulation for memory to behavioral. - Added empty mif file for memory.	cwalter	6410d 02h	/
102	changed data pitch	ustadler	6412d 07h	/
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6412d 08h	/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6412d 08h	/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6412d 08h	/
98	- Applied indenting tool.	cwalter	6412d 08h	/