URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 132

Rev	Log message	Author	Age	Path
132	Added test program for testing uart.	jlechner	6412d 21h	/
131	Changed high active resets to low active ones.	jlechner	6412d 21h	/
130	Removed obsolete line	jlechner	6412d 21h	/
129	Sample assembler program for accessing uart	jlechner	6412d 21h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6412d 21h	/
127	Changed high active resets to low active ones.	jlechner	6412d 22h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6413d 04h	/
125	Fixed vhdl bugs	trinklhar	6413d 04h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6413d 04h	/
123	Removed UART again	trinklhar	6413d 05h	/
122	Removed UART again again	trinklhar	6413d 05h	/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6413d 05h	/
120	Added UART module to memory entity	trinklhar	6413d 05h	/
119	Uart wieder ausgebaut	trinklhar	6414d 00h	/
118	insert Uart address constant	trinklhar	6414d 00h	/
117	Uart im mem_stage	trinklhar	6414d 00h	/
116	writes to uart when write to reg 0	trinklhar	6415d 06h	/
115	* empty log message *	trinklhar	6415d 20h	/
114	Uart 0.3	trinklhar	6417d 01h	/
113	Uart reset funkt	trinklhar	6417d 02h	/