URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 133

Rev	Log message	Author	Age	Path
133	- Fixed bug with ST opcodes.	cwalter	6472d 03h	/
132	Added test program for testing uart.	jlechner	6472d 03h	/
131	Changed high active resets to low active ones.	jlechner	6472d 03h	/
130	Removed obsolete line	jlechner	6472d 04h	/
129	Sample assembler program for accessing uart	jlechner	6472d 04h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6472d 04h	/
127	Changed high active resets to low active ones.	jlechner	6472d 04h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6472d 10h	/
125	Fixed vhdl bugs	trinklhar	6472d 10h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6472d 10h	/
123	Removed UART again	trinklhar	6472d 11h	/
122	Removed UART again again	trinklhar	6472d 11h	/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6472d 11h	/
120	Added UART module to memory entity	trinklhar	6472d 11h	/
119	Uart wieder ausgebaut	trinklhar	6473d 06h	/
118	insert Uart address constant	trinklhar	6473d 06h	/
117	Uart im mem_stage	trinklhar	6473d 06h	/
116	writes to uart when write to reg 0	trinklhar	6474d 13h	/
115	* empty log message *	trinklhar	6475d 03h	/
114	Uart 0.3	trinklhar	6476d 07h	/