URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 135

Rev	Log message	Author	Age	Path
135	uart_address_0 was a latch -> changed	ustadler	6437d 10h	/
134	Added second test program for testing uart.	jlechner	6437d 10h	/
133	- Fixed bug with ST opcodes.	cwalter	6437d 11h	/
132	Added test program for testing uart.	jlechner	6437d 12h	/
131	Changed high active resets to low active ones.	jlechner	6437d 12h	/
130	Removed obsolete line	jlechner	6437d 12h	/
129	Sample assembler program for accessing uart	jlechner	6437d 12h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6437d 12h	/
127	Changed high active resets to low active ones.	jlechner	6437d 12h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6437d 18h	/
125	Fixed vhdl bugs	trinklhar	6437d 18h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6437d 18h	/
123	Removed UART again	trinklhar	6437d 19h	/
122	Removed UART again again	trinklhar	6437d 19h	/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6437d 20h	/
120	Added UART module to memory entity	trinklhar	6437d 20h	/
119	Uart wieder ausgebaut	trinklhar	6438d 15h	/
118	insert Uart address constant	trinklhar	6438d 15h	/
117	Uart im mem_stage	trinklhar	6438d 15h	/
116	writes to uart when write to reg 0	trinklhar	6439d 21h	/