URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 144

Rev	Log message	Author	Age	Path
144	- IF stage now uses autogenerated VHDL files.	cwalter	6411d 21h	/
143	- Added more complex UART example.	cwalter	6411d 21h	/
142	- Added gap between characters sent and changed last character to CR.	cwalter	6411d 21h	/
141	- Added delay between characters.	cwalter	6411d 21h	/
140	- Test bench for RISE with UART.	cwalter	6411d 22h	/
139	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6411d 22h	/
138	- Fixed binary to VHDL converter.	cwalter	6411d 22h	/
137	- Added binary to VHDL converter.	cwalter	6411d 23h	/
136	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6411d 23h	/
135	uart_address_0 was a latch -> changed	ustadler	6412d 19h	/
134	Added second test program for testing uart.	jlechner	6412d 19h	/
133	- Fixed bug with ST opcodes.	cwalter	6412d 21h	/
132	Added test program for testing uart.	jlechner	6412d 21h	/
131	Changed high active resets to low active ones.	jlechner	6412d 21h	/
130	Removed obsolete line	jlechner	6412d 21h	/
129	Sample assembler program for accessing uart	jlechner	6412d 21h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6412d 21h	/
127	Changed high active resets to low active ones.	jlechner	6412d 22h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6413d 04h	/
125	Fixed vhdl bugs	trinklhar	6413d 04h	/