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Rev	Log message	Author	Age	Path
92	Added logic for inserting a nop instruction when the pipeline is cleared.	jlechner	6412d 17h	/
91	- Computed new SR values from ALU result.	cwalter	6412d 17h	/
90	Added output signal for clearing all register locks when a branch instruction is executed. This is necessary because the id stage could have locked registers for an instruction that is cleared out of the pipeline due to the branch.	jlechner	6412d 17h	/
89	Added input signal for clearing all register locks.	jlechner	6412d 17h	/
88	- Added new patch for assembler.	cwalter	6412d 18h	/
87	no message	cwalter	6412d 18h	/
86	- Added new example for a more complex loop.	cwalter	6412d 18h	/
85	Removed PC reset on clear_in signal. Clear_in only comes together with a branch, so it is sufficient branch immediately.	jlechner	6412d 20h	/
84	- PC value was wrong.	cwalter	6412d 20h	/
83	- sr_enable and lr_enable where incorrect.	cwalter	6412d 20h	/
82	- Updated drawings for memory.	cwalter	6412d 21h	/
81	- Changed to include barrel shifter.	cwalter	6412d 21h	/
80	- Fixed testbench to work with new barrel shifter.	cwalter	6412d 21h	/
79	- Added barrel shifter.	cwalter	6412d 21h	/
78	Added stall_in to sensitivity list.	jlechner	6412d 21h	/
77	- Fixed case.	cwalter	6412d 21h	/
76	- Changed order of some statements to improve readability.	cwalter	6412d 21h	/
75	- Added barrel shifter implementation.	cwalter	6412d 21h	/
74	- Fixed bug where register value used by load was passed through to write back. Correct is ALU value.	cwalter	6412d 22h	/
73	- Fixed bug where immediate value for LD_IMM_HB was placed in the upper 8bits. This is done by the execute stage.	cwalter	6412d 22h	/

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[/] - Rev 92

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