URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 63

Rev	Log message	Author	Age	Path
63	FPGA Bench mark results are added	dinesha	4495d 20h	/
62	Synthesis constraint for simplify	dinesha	4495d 20h	/
61	RTL file list are added into SVN	dinesha	4495d 21h	/
60	warning cleanup	dinesha	4495d 21h	/
59	Control path request and data are register now for better FPGA timing	dinesha	4495d 21h	/
58	Read Data is register on RD_FAST=0 case	dinesha	4495d 21h	/
57	Synthesis constraints are added	dinesha	4496d 12h	/
56	FPGA Synth optimisation	dinesha	4496d 13h	/
55	FPGA Synthesis timing optimisation	dinesha	4496d 13h	/
54	FPGA Timing Optimisation	dinesha	4499d 11h	/
53	Test bench upgradation	dinesha	4500d 11h	/
52	Documentation update for request control and transfer control block	dinesha	4500d 11h	/
51	FPGA relating timing optimisation done	dinesha	4500d 11h	/
50	Bug fix the request length is fixe	dinesha	4502d 15h	/
49	clean up	dinesha	4503d 14h	/
48	top-level cleanup	dinesha	4503d 14h	/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4503d 14h	/
46	test bench upgrade + rtl cleanup	dinesha	4505d 15h	/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4505d 19h	/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4507d 17h	/