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Rev Log message Author Age Path
15 Xilinx FPGA XC2V2000 bit files the first version. arif_endro 7187d 02h /
14 *** empty log message *** arif_endro 7192d 00h /
13 Update License arif_endro 7203d 01h /
12 Update License
Change reset signal handle
arif_endro 7203d 01h /
11 Update License
Change reset signal handle
arif_endro 7203d 01h /
10 Added script for generating cos ROM. arif_endro 7213d 04h /
9 Added documentation arif_endro 7230d 03h /
8 This commit was manufactured by cvs2svn to create tag 'okinawa_1'. 7244d 04h /
7 To view chipscope exported output using ModelSim waveform window arif_endro 7244d 04h /
6 Added Xilinx FPGA implementation (e.g. connector to ILA, ICON, and VIO) arif_endro 7245d 05h /
5 Added interface in/out and testing paralelly (e.g. square and triangular) arif_endro 7245d 05h /
4 Fix elsif and if statement arif_endro 7247d 23h /
3 This commit was manufactured by cvs2svn to create tag 'VSFR_1'. 7251d 06h /
2 Initial releases arif_endro 7251d 06h /
1 Standard project directories initialized by cvs2svn. 7251d 06h /

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