URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

[/] - Rev 16

Rev	Log message	Author	Age	Path
16	WB_TGC(5) signal fixed (indicating instruction/data fetch), coprocessor read-access bug fixed	zero_gravity	4514d 13h	/
15	new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;)	zero_gravity	4514d 17h	/
14	- corrected stupid error in access arbiter - updated minor issues	zero_gravity	4652d 13h	/
13	- corrected endianess converter for memory access - corrected error in temporal dependence detector	zero_gravity	4653d 09h	/
12	- corrected error in memory write back interface - corrected immediate/register offset for byte/halfword memory access	zero_gravity	4653d 15h	/
11		zero_gravity	4656d 19h	/
10	New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface. Ready to execute assembled ARM ASM code, arm-elf-assembler included.	zero_gravity	4656d 19h	/
9	documentation updated	zero_gravity	4746d 17h	/
8	documentation uploaded ;)	zero_gravity	4748d 11h	/
7	- new register file architecture - fixed multi-cycle op bug - architecture update	zero_gravity	4752d 09h	/
6	new core version - now with arm compatible memory interface	zero_gravity	4758d 10h	/
5	memory interface updated	zero_gravity	4809d 08h	/
4	new instruction cycle controller - interrupt call bug seems to be fixed	zero_gravity	4811d 10h	/
3		zero_gravity	4812d 18h	/
2		zero_gravity	4824d 18h	/
1	The project and the structure was created	root	4828d 01h	/