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Subversion Repositories storm_core

[/] - Rev 31

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Rev	Log message	Author	Age	Path
31	- small documentary edits - CACHE.vhd modified for better synthesis results - BUS_UNIT.vhd update to fulfill WB specs	zero_gravity	4454d 04h	/
30	- minor edits in doc	zero_gravity	4459d 04h	/
29	- specific IO area is now auto protected - Wishbone compatibility extended - cache flush optimized - accelerated bus cycles due to less overhead	zero_gravity	4460d 04h	/
28	- bugfix in pipeline re-sync of d/i-cache - optimized bus unit - minor edits... ^^	zero_gravity	4471d 07h	/
27	updated "sim" folder - error in testbench environment -> old components -> weren't compatible to new core version anymore => FIXED! ;) - thanks to Pratip Mukherjee	zero_gravity	4475d 06h	/
26	bug fixes: - change in priority for cache miss/dirty/io_access - memory based pc modifications - removed internal timer	zero_gravity	4476d 06h	/
25	bug-fix in cache component: -> error in cache page-access history manager	zero_gravity	4484d 14h	/
24	- changed back to original oc svn folder structure - bug-fix in documentary - WB_ERR_I signal added to terminate wishbone bus access - bug-fix: system mode register set and privs	zero_gravity	4485d 13h	/
23		zero_gravity	4485d 13h	/
22	changed back to original svn folder structure	zero_gravity	4485d 14h	/
21	smaller, faster, better ;) * bug-fix: load-multiple instructions * new cache-control system * direct-accessible IO area can be specified * extended demo implementation	zero_gravity	4492d 09h	/
20	- update of data sheet -> note for system memory map layout and d-cache configuration	zero_gravity	4508d 03h	/
19	- simulation test bench added - example for compatible wishbone fabric/SoC added - block transfers from user bank updated	zero_gravity	4508d 07h	/
18	makefile update to ensure no thumb code is generated	zero_gravity	4513d 12h	/
17	small synthesis-friendly update of memory components	zero_gravity	4516d 05h	/
16	WB_TGC(5) signal fixed (indicating instruction/data fetch), coprocessor read-access bug fixed	zero_gravity	4516d 07h	/
15	new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;)	zero_gravity	4516d 12h	/
14	- corrected stupid error in access arbiter - updated minor issues	zero_gravity	4654d 08h	/
13	- corrected endianess converter for memory access - corrected error in temporal dependence detector	zero_gravity	4655d 04h	/
12	- corrected error in memory write back interface - corrected immediate/register offset for byte/halfword memory access	zero_gravity	4655d 09h	/

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Subversion Repositories storm_core

[/] - Rev 31

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