OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 247

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
247 Added the cpu mapped verilog creep 5509d 22h /
246 Added some older files plus the first syn script creep 5511d 02h /
245 Added a few dirs for the synthesis creep 5511d 02h /
244 Added a few dirs for the synthesis creep 5511d 02h /
243 Fixing STA_IDY bug creep 5552d 19h /
242 Bug regardind the STA_IDY opcode creep 5552d 23h /
241 Fixed half the problem with strange STA behavior. creep 5553d 22h /
240 Finally fixed the decimal mode! creep 5554d 00h /
239 Zero flag fixed for SBC while in Decimal Mode. Bug #34. gabrieloshiro 5554d 01h /
238 ALU file is linted. creep 5556d 22h /
237 Added a preliminary collision detection logic. creep 5557d 23h /
236 Added the video converter testbench to the repository. creep 5558d 02h /
235 Bug #60: added a brief simulation to the video_converter module. creep 5558d 20h /
234 SBC Decimal mode 100% verified. creep 5563d 22h /
233 ADC and SBC are 100% verified in regular mode. Decimal mode still missing. creep 5564d 02h /
232 New video test. creep 5565d 20h /
231 Minor bugs fixed. gabrieloshiro 5565d 21h /
230 Changed TIA behavior. It is now pixel-based. creep 5565d 21h /
229 Created a one-line pattern. creep 5566d 02h /
228 gabrieloshiro 5566d 02h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.