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16 Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.		 earlz 4465d 16h /
15 Added README, LICENSE, and the (so far not created) incdec component earlz 4467d 13h /
14 Added ALU with all the operations we'll need. Synthesizes as well trivially earlz 4467d 21h /
13 Forgot about the new library I added earlz 4468d 00h /
12 registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD		 earlz 4468d 01h /
11 Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge earlz 4471d 14h /
10 Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs earlz 4471d 14h /
9 Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench earlz 4471d 22h /
8 Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing		 earlz 4472d 22h /
7 Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)		 earlz 4472d 23h /
6 Reworked memory code to hopefully synthesize better earlz 4473d 03h /
5 Modified registerfile to be dual-port for both read and write earlz 4473d 14h /
4 Added internal memory interface
Updated design		 earlz 4473d 22h /
3 Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming		 earlz 4474d 14h /
2 Initial commit earlz 4474d 16h /
1 The project and the structure was created root 4474d 18h /

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