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Subversion Repositories usb_dongle_fpga

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Rev Log message Author Age Path
37 Initial commit of EPCS1 (FPGA configuration memory) programmer to update dongle firmware nuubik 5998d 20h /
36 Initial commit of EPCS1 (FPGA configuration memory) programmet to update dongle firmware nuubik 5998d 20h /
35 Fixed postcode nibbles swapped issue added D0 D11 commands for IO port 0x88
(enable/disable memory reads)		 nuubik 5998d 20h /
34 For download of v5 dongle tool and manual nuubik 6000d 21h /
33 For download of v5 web release nuubik 6000d 22h /
32 For download of v5 datasheet nuubik 6000d 22h /
31 Newest available schematic nuubik 6001d 15h /
30 Fixed some typos in document nuubik 6001d 15h /
29 Added link to cheap ($40) ByteBlaster clone cable to update notice and fix'ed help typo nuubik 6001d 15h /
28 Quartus project files for HW code 5 project files nuubik 6002d 15h /
27 Initial commit of post code logger block and fifo used in the logger nuubik 6002d 15h /
26 Added flash_sts status check as flash_sts pin works now (flas_sts had 2 inputs pins what caused it not to work propery now one is highZ output).
Added post code logger block and LPC IO write flow control and flash lock when flash is programmed		 nuubik 6002d 15h /
25 Added flash_sts status check as flash_sts pin works now (flas_sts had 2 inputs pins what caused it not to work propery now one is highZ output).
Added 64K byte block read when read length is 0		 nuubik 6002d 15h /
24 Added changes for new dongle HW code 5 features nuubik 6002d 15h /
23 Inlined dongle spesific Uspp code to dongle.py script separate Uspp is no longer needed.
Forced serial port to hw flow control mode.
Added support for new dongle HW code 5 to support fast read and fast write modes		 nuubik 6002d 16h /
22 Inlined dongle spesific Uspp code to dongle.py script separate Uspp is no longer needed nuubik 6002d 16h /
21 This commit was manufactured by cvs2svn to create tag 'version_1_4'. 6015d 18h /
20 Fix'ed TAR cycle second part this is not critical update nuubik 6015d 18h /
19 Fix'ed cycle type init code copy/pase mistake nuubik 6015d 20h /
18 Fixed in reset init of some trigers (this should not have generated extra hardware in FPGA but just to be on the safe side) nuubik 6016d 19h /

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