URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

[/] - Rev 119

Rev	Log message	Author	Age	Path
119	cleanup	ultro	2827d 20h	/
118	cleanup	ultro	2827d 20h	/
117	reset polarity in mig_b.prj for ddr2 was wrong , should be high	ultro	2875d 00h	/
116	fix path of the axi rom module	ultro	2888d 19h	/
115	update for synth slack	ultro	2889d 13h	/
114	update cosmetic	ultro	2889d 14h	/
113	updates to take acu appart	ultro	2889d 14h	/
112	Added the prj missing files	ultro	2893d 03h	/
111	added comment	ultro	2909d 13h	/
110	updated MCS files to be downloaded to nexys4 DDR	ultro	2909d 13h	/
109	update for nexys 4 ddr	ultro	2909d 13h	/
108	update xdc for nexys 4 ddr	ultro	2909d 13h	/
107	crossbar update	ultro	2909d 13h	/
106	update core netlist	ultro	2909d 13h	/
105	migration nexys ddr	ultro	2909d 15h	/
104	iadd rstgen and clk wiard for ddr nexys4 TOP	ultro	2916d 15h	/
103	commit top for 128mbyte nexys4 ddr version	ultro	2926d 04h	/
102	committed 128mbytes boot code for nexys4 ddr	ultro	2926d 04h	/
101	add ddr interface mig7 xilinx xci ip	ultro	2926d 18h	/
100	add crossbar for nexys4 ddr with 128megabyte ram window	ultro	2926d 18h	/