URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 36

Rev	Log message	Author	Age	Path
36		unneback	5260d 15h	/
35	work for limited test case	unneback	5260d 22h	/
34	added	unneback	5260d 23h	/
33	work for limited test case, no cke inhibit for fifo empty	unneback	5261d 01h	/
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5264d 05h	/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5265d 22h	/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5265d 22h	/
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5269d 22h	/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5270d 00h	/
27		unneback	5273d 15h	/
26	compiles OK, not simulated	unneback	5275d 15h	/
25		unneback	5275d 17h	/
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5276d 04h	/
23	Removed redundant code.	mikaeljf	5283d 21h	/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5285d 17h	/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5289d 20h	/
20	Minor update of sdc-file.	mikaeljf	5291d 22h	/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5298d 02h	/
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5298d 23h	/
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5301d 22h	/