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Rev Log message Author Age Path
20 Switched parameter order. rherveille 8370d 06h /
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8370d 07h /
18 Removed files. They are not used anymore. rherveille 8399d 04h /
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)		 rherveille 8399d 04h /
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8426d 11h /
15 Created directory structure (documentation, vhdl, verilog) rherveille 8462d 00h /
14 Added CLUT bank switching.
Replaced multiplier with simple counters.
Fixed timing bug.		 rherveille 8462d 19h /
13 Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore. rherveille 8463d 08h /
12 Added new top-level and sub-level (vga_and_clut.vhd & csm.vhd);
adds color-lookup-table to the VGA core (i.e. on-chip CLUT).
Ram generation has been tested with Altera and Xilinx parts.		 rherveille 8472d 12h /
11 Major bug fixes in Wishbone Master and ColorProcessor blocks.
Core did not respond correctly to delayed ACK_I signals.

Added built-in Color Lookup Tables.		 rherveille 8472d 12h /
10 Design now uses Xilinx-BlockRAMs instead of selectRAM rherveille 8479d 03h /
9 no message rherveille 8479d 20h /
8 Revised core. Removed unused signals rherveille 8485d 04h /
7 revised counter.vhd rherveille 8489d 06h /
6 no message rherveille 8490d 06h /
5 Fixed a bug in wishbone master. Updated simulation files also rherveille 8494d 06h /
4 changed wishbone address sections. rherveille 8505d 06h /
3 This commit was manufactured by cvs2svn to create tag 'beta'. 8518d 11h /
2 initial release rherveille 8518d 11h /
1 Standard project directories initialized by cvs2svn. 8518d 11h /

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