OpenCores
URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] - Rev 28

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8232d 21h /
27 Added 32bpp
Fixed some typos
Added bandwidth section		 rherveille 8232d 21h /
26 Added 32bpp tests rherveille 8232d 21h /
25 C-include file.
Initial release		 rherveille 8299d 14h /
24 Updated testbench for VGA/LCD Core version 2.0 rherveille 8306d 17h /
23 Added Copyright/Licence header rherveille 8307d 13h /
22 VGA Core v2.0
Document revision 0.7		 rherveille 8327d 09h /
21 VGA Core v2.0
Document revision 0.7		 rherveille 8327d 10h /
20 Switched parameter order. rherveille 8336d 14h /
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8336d 15h /
18 Removed files. They are not used anymore. rherveille 8365d 12h /
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)		 rherveille 8365d 12h /
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8392d 19h /
15 Created directory structure (documentation, vhdl, verilog) rherveille 8428d 08h /
14 Added CLUT bank switching.
Replaced multiplier with simple counters.
Fixed timing bug.		 rherveille 8429d 03h /
13 Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore. rherveille 8429d 16h /
12 Added new top-level and sub-level (vga_and_clut.vhd & csm.vhd);
adds color-lookup-table to the VGA core (i.e. on-chip CLUT).
Ram generation has been tested with Altera and Xilinx parts.		 rherveille 8438d 20h /
11 Major bug fixes in Wishbone Master and ColorProcessor blocks.
Core did not respond correctly to delayed ACK_I signals.

Added built-in Color Lookup Tables.		 rherveille 8438d 20h /
10 Design now uses Xilinx-BlockRAMs instead of selectRAM rherveille 8445d 11h /
9 no message rherveille 8446d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.