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Rev Log message Author Age Path
55 Initial release. rherveille 7739d 01h /
54 Added DVI tests rherveille 7739d 01h /
53 Fixed some Wishbone RevB.3 related bugs.
Changed layout of the core. Blocks are located more logically now.
Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.
rherveille 7739d 06h /
52 Numerous updates and added checks rherveille 7739d 06h /
51 Forgot to change document revision number rherveille 7787d 01h /
50 Forgot to change document revision rherveille 7787d 01h /
49 Added WISHBONE revB.3 signals rherveille 7787d 02h /
48 WISHBONE revB.3 signals added rherveille 7787d 02h /
47 Added wb_b3_check
Removed ud_cnt, ro_cnt
rherveille 7787d 22h /
46 Added WISHBONE revB.3 sanity checks rherveille 7787d 22h /
45 Changed timing generator; made it smaller and easier. rherveille 7788d 03h /
44 Changed timing section in VGA core, changed testbench accordingly.
Fixed bug in 'timing check' test.
rherveille 7788d 03h /
43 Added WISHBONE revB.3 Registered Feedback Cycles support rherveille 7788d 18h /
42 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8121d 04h /
41 specs version 1.1 rherveille 8121d 04h /
40 no message rherveille 8121d 04h /
39 Changed video timing generator.
Changed wishbone master vertical gate count code.
Fixed a potential bug in the wishbone slave (cursor color register readout).
rherveille 8121d 06h /
38 Changed testbench to reflect modified VGA timing generator. rherveille 8121d 06h /
37 Fixed a potential reset bug in the hint & vint generation. rherveille 8136d 09h /
36 Fixed two small bugs that only showed up when the hardware cursors were disabled rherveille 8144d 11h /

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