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Rev Log message Author Age Path
33 revert to rev 1 as rev 2 seems unreadable binary file checkin problem ? bporcella 6145d 01h /
32 fixed bugs and augmented instruction test.
ex de hl bug fixed thanks Howard Harte
ret condition (ret not taken bug) thanks - Stephen Warren
bporcella 6153d 00h /
31 some fixes found in synthesis bporcella 7369d 00h /
30 test executes cleanly bporcella 7376d 05h /
29 logic movd to z80_sram.v bporcella 7376d 05h /
28 logic movd to z80_bist_logic.v bporcella 7376d 06h /
27 Instruction test (with interrupts) runs!!! bporcella 7376d 06h /
26 inst test got to the worked macro bporcella 7382d 17h /
25 instruction test getting to final stages bporcella 7384d 21h /
24 testbed built and verification in progress bporcella 7390d 02h /
23 testbed built and verification in progress bporcella 7390d 05h /
22 testbed files bporcella 7390d 05h /
21 build script bporcella 7390d 05h /
20 check in test files and assembler manual bporcella 7390d 05h /
19 chckin for ease of use bporcella 7390d 05h /
18 test lint on core bporcella 7405d 22h /
17 first core build bporcella 7405d 23h /
16 re-named bporcella 7406d 00h /
15 file not of general interest bporcella 7407d 05h /
14 first cut revision bporcella 7409d 20h /

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