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Rev Log message Author Age Path
63 Remove historical output ports that are no longer used. rehayes 5239d 15h /
62 Cleanup implicit wire declarations. rehayes 5239d 15h /
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5246d 14h /
60 Add ability at insert wait states on RAM access rehayes 5246d 15h /
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5246d 15h /
58 WISHBONE Bus update. rehayes 5298d 14h /
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5298d 17h /
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5314d 18h /
55 Minor change to instruction set details. rehayes 5314d 18h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5314d 18h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5314d 18h /
52 Minor changes to aide waveform debug rehayes 5314d 18h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5330d 14h /
50 incremental update to match status bit changes rehayes 5330d 14h /
49 First pass with instruction set details rehayes 5330d 15h /
48 Update for SBC ana ADC condition code changes rehayes 5330d 15h /
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5330d 15h /
46 Update to remove stack registers and add new register text. rehayes 5362d 13h /
45 Update to remove stack registers and add new register text. rehayes 5362d 13h /
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5364d 12h /

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