| Rev |
Log message |
Author |
Age |
Path |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
3145d 08h |
/ |
| 49 |
Added some documentation to make the read and write calls easier to understand. |
dgisselq |
3154d 08h |
/ |
| 48 |
Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ... |
dgisselq |
3156d 10h |
/ |
| 47 |
Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.) |
dgisselq |
3156d 10h |
/ |
| 46 |
This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles. |
dgisselq |
3156d 10h |
/ |
| 45 |
Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference. |
dgisselq |
3160d 06h |
/ |
| 44 |
NELM parameter adjusted to reflect the maximum number of lines the compressed
scope can handle: 31, not 32. |
dgisselq |
3160d 06h |
/ |
| 43 |
Commentary changes only, no substance. |
dgisselq |
3160d 06h |
/ |
| 42 |
Minor changes. |
dgisselq |
3160d 06h |
/ |
| 41 |
Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier. |
dgisselq |
3160d 06h |
/ |
| 40 |
This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb. |
dgisselq |
3161d 17h |
/ |
| 39 |
An attempt at a bugfix. We'll see if this works any better downstream. |
dgisselq |
3163d 12h |
/ |
| 38 |
Updated to remove the build dependence upon ZipCPU. |
dgisselq |
3163d 16h |
/ |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
3164d 10h |
/ |
| 36 |
A linker script, appropriate to the XuLA25-LX25 SoC. |
dgisselq |
3164d 11h |
/ |
| 35 |
Updates the memory testing program to work successfully with the Gnu build
tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from
Binutils. |
dgisselq |
3164d 11h |
/ |
| 34 |
Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.) |
dgisselq |
3168d 06h |
/ |
| 33 |
Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip. |
dgisselq |
3168d 08h |
/ |
| 32 |
Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate. |
dgisselq |
3168d 08h |
/ |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3168d 08h |
/ |
