| Rev |
Log message |
Author |
Age |
Path |
| 20 |
Added a quick README to the debugger directory. |
dgisselq |
3380d 10h |
/ |
| 19 |
Here's the outlines of a debugger. |
dgisselq |
3380d 10h |
/ |
| 18 |
A couple of changes: Registers can now be changed via the debug interface.
Also, in anticipation of being able to interrupt the break the processor,
the CPU now exports an interrupt line to the external environment to tell
when it has been halted. Thus, if it gets halted by a break instruction,
the ZipSystem will interrupt whatever's in its environment so that the
debugger can come and examine its state.
Oh, and one other: because you can't examine the state of the CPU without
halting it, I modified the debug control register to export the four
useful flags: break-enable, interrupts enabled, and sleep (step comes for
free in this implementation). |
dgisselq |
3380d 11h |
/ |
| 17 |
The ZOPCODES function zipi_to_string (ZIP CPU instruction to string, part of
the machine code dump) was adjusted to have closer to a fixed width output.
It no longer uses tab characters, which can have an unreliable effect. |
dgisselq |
3380d 11h |
/ |
| 16 |
The assembler now supports:
1. Multiple data elements on a line. These are lines like:
WORD 5,8,4,1
which place the words 5, 8, 4, and 1 directly into the object code to be
referenced as data. Prior to this release, these lines would assemble
properly but only place '5' as a data element into the object code.
2. The '-E' preprocessor only directive is now supported to produce output
from the preprocessor and see what is (or is not) happening there.
3. The preprocessor now validly places "#line" comments into the file, which
the assembler picks up and uses in it's error codes. These help identify
where errors took place.
4. Zasm now looks for the preprocessor (zpp) in the same directory zasm was
run from, using the same directory prefix as zasm, whenever zasm is given such
a directory prefix.
And ... perhaps other things I've forgotten about. |
dgisselq |
3381d 17h |
/ |
| 15 |
Updated the core CPUOPS module to make certain that the carry was properly
set on right shifts. (Carry is then the last bit shifted out to the right,
and has no relation to the high order bits of the word.) Also fixed a bug
in the busdelay.v file that prevented our Quad SPI flash controller from
working. (This bug fix has not yet been tested ...) Our test.S program, the
closest thing we have to a regression test and found in the sw/zasm directory,
still successfully passes in Verilator. |
dgisselq |
3384d 00h |
/ |
| 14 |
Removing zasm.cpp--the old assembler that never worked well. |
dgisselq |
3384d 00h |
/ |
| 13 |
Finally! The beginnings of the new assembler. It's not really polished yet,
and it is quite clunky, but it works!! (Lots of bugs and features left to
fix/implement: #include, #define macro(), #line tracking through the
preprocessor, a means of finding include files (and the preprocessor!) and
more. But, as a beginning, the basics are functinoal. |
dgisselq |
3384d 00h |
/ |
| 12 |
Bunch of changes while trying to get a hello world program:
1. Right shifts by 32 or more now result in zero, or all of the top bit in the
case of ASRs.
2. zdump now properly includes addresses with dumped lines.
3. zparser now properly handles immediate values via the .DAT instruction. |
dgisselq |
3398d 15h |
/ |
| 11 |
This version works on an FPGA!!!
(Or at least the wdt.S program passes ...) |
dgisselq |
3399d 00h |
/ |
| 10 |
Here's the watchdog timer code, as well as some pictures of the register
set. |
dgisselq |
3399d 13h |
/ |
| 9 |
This checkin is the result of a watchdog timer test, and everything it took
to get the watchdog timer working. The timer function was simplified,
although it now uses a touch more resources--being able to count down 31
bits instead of 30. The parser was modified, since it couldn't handle
storing to register plus offsets like it was supposed to be able to. The
testbench, zippy_tb, was modified to accept an assembled machine code file
such as I might place on a board to test it.
Lots of work to get it working.
Looking at the files below, it looks like I'll need a second check in to check
in the watchdog timer test itself. |
dgisselq |
3399d 13h |
/ |
| 8 |
Fixed the rotate left instruction to work in the zasm parser, and to be
properly referenced in the simulator. The instruction set documentation was
also adjusted to reflect what the CPU actually does. |
dgisselq |
3399d 20h |
/ |
| 7 |
Here's the iset.html file that was at one time in the gfx directory, but
which could not be moved due to a bad gateway error ... (Grrr). |
dgisselq |
3399d 21h |
/ |
| 6 |
Trying to move iset.html from gfx directory. |
dgisselq |
3399d 21h |
/ |
| 5 |
Updated colors in the graphics. |
dgisselq |
3399d 21h |
/ |
| 4 |
|
dgisselq |
3399d 21h |
/ |
| 3 |
Rebuilt the pipefetch (instruction fetch/cache module) so that it will
let go of the bus if the memory unit wants it to execute an instruction.
Pipefetch will then grab the bus back whtn the memory unit is done, so things
otherwise continue as they were before.
Other tweaks were made to try to reduce code complexity. |
dgisselq |
3399d 21h |
/ |
| 2 |
An initial load. No promises of what works or not, but this is where the
project is at. |
dgisselq |
3400d 14h |
/ |
| 1 |
The project and the structure was created |
root |
3400d 19h |
/ |
