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4 dgisselq 3270d 14h /
3 Rebuilt the pipefetch (instruction fetch/cache module) so that it will
let go of the bus if the memory unit wants it to execute an instruction.
Pipefetch will then grab the bus back whtn the memory unit is done, so things
otherwise continue as they were before.

Other tweaks were made to try to reduce code complexity.
dgisselq 3270d 14h /
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 3271d 07h /
1 The project and the structure was created root 3271d 12h /

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