| Rev |
Log message |
Author |
Age |
Path |
| 80 |
Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining. |
dgisselq |
3242d 07h |
/ |
| 79 |
Adjusted the opcodes for NOOP, BREAK, and LOCK. |
dgisselq |
3246d 11h |
/ |
| 78 |
Found/corrected annoying bug in floating point documentation of the opcode
table. |
dgisselq |
3246d 11h |
/ |
| 77 |
First check-in: the test bench for the divide instruction. |
dgisselq |
3247d 10h |
/ |
| 76 |
The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions. |
dgisselq |
3247d 10h |
/ |
| 75 |
Modified for VLIW instructions. |
dgisselq |
3247d 10h |
/ |
| 74 |
Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files. |
dgisselq |
3247d 10h |
/ |
| 73 |
Documentations updates. |
dgisselq |
3247d 10h |
/ |
| 72 |
Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit. |
dgisselq |
3247d 10h |
/ |
| 71 |
This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus. |
dgisselq |
3247d 10h |
/ |
| 70 |
Updated the assembler support files, zopcodes in particular, to handle
the disassembly of the new very long instruction word codes. |
dgisselq |
3247d 10h |
/ |
| 69 |
This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture. |
dgisselq |
3253d 15h |
/ |
| 68 |
Updated specification, includes well illustrated pipeline discussion. |
dgisselq |
3288d 15h |
/ |
| 67 |
Includes timing diagrams in support of a very descriptive specification section. |
dgisselq |
3288d 15h |
/ |
| 66 |
Adjusted the support for the DEBUG_SCOPE within these so that it can be
compiled in, or not, based upon an external build configuration file: cpudefs.v.
That allows me to make that file project specific, while the rest of the CPU
is shared among all projects. |
dgisselq |
3314d 15h |
/ |
| 65 |
Lots of logic simplifications to the core, in addition to better support for
illegal instruction detection and bus error detection. The biggest change
had to deal with pushing the debug write interface into the ALU write
processing path. This simplifies the logic of adjusting the PC and CC
registers primarily, but also any writes to other registers. It also delays
these register writes by a clock, but since the debug interface is already
ridiculously slow I doubt that matters any. |
dgisselq |
3314d 15h |
/ |
| 64 |
Shuffled some comments into here from elsewhere. |
dgisselq |
3314d 15h |
/ |
| 63 |
Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine. |
dgisselq |
3314d 15h |
/ |
| 62 |
Simplified the subtraction logic, so the carry bit no longer depends on
a separate 32-bit operation but becomes part of the subtract operation. |
dgisselq |
3314d 15h |
/ |
| 61 |
Simplified the bus delay logic. Depends upon the stall line being irrelevant
outside of a bus cycle. |
dgisselq |
3314d 15h |
/ |
