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133 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7662d 13h /.
132 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7662d 13h /.
131 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7662d 13h /.
130 mbist signals updated according to newest convention markom 7662d 13h /.
129 Error counters changed. mohor 7678d 22h /.
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7678d 22h /.
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7678d 22h /.
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7679d 18h /.
125 Synchronization changed, error counters fixed. mohor 7684d 00h /.
124 ALTERA_RAM supported. mohor 7704d 07h /.
123 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7711d 12h /.
122 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7711d 12h /.
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7711d 12h /.
120 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7720d 09h /.
119 Artisan RAMs added. mohor 7720d 09h /.
118 Artisan RAM fixed (when not using BIST). mohor 7720d 09h /.
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7720d 09h /.
116 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7726d 03h /.
115 Artisan ram instances added. simons 7726d 03h /.
114 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7753d 04h /.

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