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[/] [.] - Rev 144

Rev	Log message	Author	Age	Path
144	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7468d 19h	/.
143	Bit acceptance_filter_mode was inverted.	igorm	7468d 19h	/.
142	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7487d 18h	/.
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7487d 18h	/.
140	I forgot to thange one signal name.	igorm	7542d 16h	/.
139	Signal bus_off_on added.	igorm	7542d 16h	/.
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7581d 19h	/.
137	Header changed.	mohor	7581d 19h	/.
136	Error counters changed.	mohor	7581d 19h	/.
135	Header changed.	mohor	7581d 19h	/.
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7689d 17h	/.
133	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7696d 04h	/.
132	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7696d 04h	/.
131	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7696d 04h	/.
130	mbist signals updated according to newest convention	markom	7696d 04h	/.
129	Error counters changed.	mohor	7712d 12h	/.
128	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7712d 13h	/.
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7712d 13h	/.
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7713d 09h	/.
125	Synchronization changed, error counters fixed.	mohor	7717d 15h	/.