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[/] [.] - Rev 147

Rev	Log message	Author	Age	Path
147	Interrupt is always cleared for one clock after the irq register is read. This fixes problems when CPU is using IRQs that are edge triggered.	igorm	7288d 05h	/.
146	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7288d 10h	/.
145	Arbitration bug fixed.	igorm	7288d 10h	/.
144	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7435d 02h	/.
143	Bit acceptance_filter_mode was inverted.	igorm	7435d 02h	/.
142	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7454d 01h	/.
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7454d 01h	/.
140	I forgot to thange one signal name.	igorm	7508d 23h	/.
139	Signal bus_off_on added.	igorm	7508d 23h	/.
138	Header changed. Address latched to posedge. bus_off_on signal added.	mohor	7548d 02h	/.
137	Header changed.	mohor	7548d 02h	/.
136	Error counters changed.	mohor	7548d 02h	/.
135	Header changed.	mohor	7548d 02h	/.
134	Active high/low problem when Altera devices are used. Bug fixed by Rojhalat Ibrahim.	mohor	7656d 00h	/.
133	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7662d 11h	/.
132	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7662d 11h	/.
131	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7662d 11h	/.
130	mbist signals updated according to newest convention	markom	7662d 11h	/.
129	Error counters changed.	mohor	7678d 19h	/.
128	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7678d 20h	/.