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Rev Log message Author Age Path
155 rd_info_pointer fixed (fifo_empty was used instead of info_empty). igorm 7152d 08h /.
154 irq is cleared after the release_buffer command. This bug was entered with
changes for the edge triggered interrupts.		 igorm 7252d 01h /.
153 Arbitration capture register changed. SW reset (setting the reset_mode bit)
doesn't work as HW reset.		 igorm 7259d 21h /.
152 Fixes for compatibility after the SW reset. igorm 7264d 04h /.
151 When CAN was reset by setting the reset_mode signal in mode register, it
was possible that CAN was blocked for a short period of time. Problem
occured very rarly.		 igorm 7266d 22h /.
150 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7285d 22h /.
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7285d 22h /.
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7288d 05h /.
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7288d 05h /.
146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7288d 10h /.
145 Arbitration bug fixed. igorm 7288d 10h /.
144 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7435d 02h /.
143 Bit acceptance_filter_mode was inverted. igorm 7435d 02h /.
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7454d 00h /.
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7454d 00h /.
140 I forgot to thange one signal name. igorm 7508d 23h /.
139 Signal bus_off_on added. igorm 7508d 23h /.
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7548d 02h /.
137 Header changed. mohor 7548d 02h /.
136 Error counters changed. mohor 7548d 02h /.

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