OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [.] - Rev 127

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
127 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7476d 09h /.
126 run_sim.scr renamed to run_sim for VATS. mohor 7476d 09h /.
125 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7478d 06h /.
124 Display for VATS added. mohor 7478d 06h /.
123 All flipflops are reset. mohor 7478d 06h /.
122 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7481d 06h /.
121 Port signals are all set to zero after reset. mohor 7481d 06h /.
120 test stall_test added. mohor 7481d 09h /.
119 cpu_stall_o activated as soon as bp occurs. mohor 7481d 10h /.
118 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7483d 05h /.
117 Define name changed. mohor 7483d 05h /.
116 Data latching changed when testing WB. mohor 7483d 06h /.
115 More debug data added. mohor 7483d 09h /.
114 CRC generation iand verification in bench changed. mohor 7483d 11h /.
113 IDCODE test improved. mohor 7483d 12h /.
112 dbg_tb_defines.v not used. mohor 7484d 06h /.
111 Define tap_defines.v added to test bench. mohor 7484d 07h /.
110 Waiting for "ready" improved. mohor 7484d 07h /.
109 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7484d 12h /.
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7484d 12h /.

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.