URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [.] - Rev 15

Rev	Log message	Author	Age	Path
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8378d 16h	/.
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8378d 16h	/.
13	Fixed some synthesis warnings.	rherveille	8389d 20h	/.
12	no message	rherveille	8395d 12h	/.
11	Changed RST_LVL define to parameter.	rherveille	8398d 19h	/.
10	Created new directory structure. Added Verilog version.	rherveille	8420d 16h	/.
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8490d 11h	/.
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8490d 11h	/.
7	added some remarks, fixed some sensitivity lists	rherveille	8559d 14h	/.
6	fixed typo txt -> txr	rherveille	8563d 18h	/.
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8570d 16h	/.
4	WISHBONE I2C Master Core: initial release	rherveille	8622d 19h	/.
3	This commit was manufactured by cvs2svn to create tag 'first'.		8684d 18h	/.
2	initial release	rherveille	8684d 18h	/.
1	Standard project directories initialized by cvs2svn.		8684d 18h	/.