URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [.] - Rev 17

Rev	Log message	Author	Age	Path
17	C-include file. Initial release	rherveille	8289d 00h	/.
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8301d 00h	/.
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8305d 22h	/.
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8305d 22h	/.
13	Fixed some synthesis warnings.	rherveille	8317d 02h	/.
12	no message	rherveille	8322d 18h	/.
11	Changed RST_LVL define to parameter.	rherveille	8326d 01h	/.
10	Created new directory structure. Added Verilog version.	rherveille	8347d 22h	/.
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8417d 17h	/.
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8417d 17h	/.
7	added some remarks, fixed some sensitivity lists	rherveille	8486d 20h	/.
6	fixed typo txt -> txr	rherveille	8491d 00h	/.
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8497d 22h	/.
4	WISHBONE I2C Master Core: initial release	rherveille	8550d 01h	/.
3	This commit was manufactured by cvs2svn to create tag 'first'.		8612d 00h	/.
2	initial release	rherveille	8612d 00h	/.
1	Standard project directories initialized by cvs2svn.		8612d 00h	/.