URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [.] - Rev 23

Rev	Log message	Author	Age	Path
23	* empty log message *	rherveille	8052d 06h	/.
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8062d 11h	/.
21	no message	rherveille	8148d 12h	/.
20	Added Appendix A	rherveille	8148d 12h	/.
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8152d 08h	/.
18	no message	rherveille	8179d 04h	/.
17	C-include file. Initial release	rherveille	8267d 09h	/.
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8279d 08h	/.
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8284d 07h	/.
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8284d 07h	/.
13	Fixed some synthesis warnings.	rherveille	8295d 11h	/.
12	no message	rherveille	8301d 02h	/.
11	Changed RST_LVL define to parameter.	rherveille	8304d 10h	/.
10	Created new directory structure. Added Verilog version.	rherveille	8326d 06h	/.
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8396d 01h	/.
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8396d 01h	/.
7	added some remarks, fixed some sensitivity lists	rherveille	8465d 04h	/.
6	fixed typo txt -> txr	rherveille	8469d 08h	/.
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8476d 06h	/.
4	WISHBONE I2C Master Core: initial release	rherveille	8528d 09h	/.