URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [.] - Rev 25

Rev	Log message	Author	Age	Path
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7987d 06h	/.
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7987d 06h	/.
23	* empty log message *	rherveille	8114d 11h	/.
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8124d 16h	/.
21	no message	rherveille	8210d 17h	/.
20	Added Appendix A	rherveille	8210d 17h	/.
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8214d 14h	/.
18	no message	rherveille	8241d 09h	/.
17	C-include file. Initial release	rherveille	8329d 14h	/.
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8341d 13h	/.
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8346d 12h	/.
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8346d 12h	/.
13	Fixed some synthesis warnings.	rherveille	8357d 16h	/.
12	no message	rherveille	8363d 08h	/.
11	Changed RST_LVL define to parameter.	rherveille	8366d 15h	/.
10	Created new directory structure. Added Verilog version.	rherveille	8388d 12h	/.
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8458d 07h	/.
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8458d 07h	/.
7	added some remarks, fixed some sensitivity lists	rherveille	8527d 09h	/.
6	fixed typo txt -> txr	rherveille	8531d 13h	/.