URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [.] - Rev 34

Rev	Log message	Author	Age	Path
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7831d 06h	/.
33	Fixed a bug in the Command Register declaration.	rherveille	7853d 15h	/.
32	Multi-master capabilities added to the core. Changed documentation accordingly. Updated some timing diagrams.	rherveille	7863d 15h	/.
31	Core is now a Multimaster I2C controller.	rherveille	7867d 16h	/.
30	Small code simplifications	rherveille	7867d 16h	/.
29	Core is now a Multimaster I2C controller	rherveille	7867d 17h	/.
28	* empty log message *	rherveille	7893d 10h	/.
27	Cleaned up code	rherveille	7893d 10h	/.
26	* empty log message *	rherveille	7896d 18h	/.
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7924d 14h	/.
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7924d 14h	/.
23	* empty log message *	rherveille	8051d 19h	/.
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8062d 00h	/.
21	no message	rherveille	8148d 01h	/.
20	Added Appendix A	rherveille	8148d 01h	/.
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8151d 22h	/.
18	no message	rherveille	8178d 17h	/.
17	C-include file. Initial release	rherveille	8266d 22h	/.
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8278d 21h	/.
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8283d 20h	/.