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[/] [.] - Rev 37

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Rev Log message Author Age Path
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7756d 02h /.
36 Fixed cmd_ack generation item (no bug). rherveille 7871d 03h /.
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7904d 17h /.
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7908d 15h /.
33 Fixed a bug in the Command Register declaration. rherveille 7931d 01h /.
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7941d 00h /.
31 Core is now a Multimaster I2C controller. rherveille 7945d 01h /.
30 Small code simplifications rherveille 7945d 01h /.
29 Core is now a Multimaster I2C controller rherveille 7945d 02h /.
28 *** empty log message *** rherveille 7970d 19h /.
27 Cleaned up code rherveille 7970d 19h /.
26 *** empty log message *** rherveille 7974d 03h /.
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 8001d 23h /.
24 Fixed some reported minor start/stop generation timing issuess. rherveille 8001d 23h /.
23 *** empty log message *** rherveille 8129d 05h /.
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8139d 10h /.
21 no message rherveille 8225d 10h /.
20 Added Appendix A rherveille 8225d 10h /.
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8229d 07h /.
18 no message rherveille 8256d 03h /.

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