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[/] [.] - Rev 38

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Rev Log message Author Age Path
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7625d 05h /.
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7661d 21h /.
36 Fixed cmd_ack generation item (no bug). rherveille 7776d 22h /.
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7810d 12h /.
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7814d 10h /.
33 Fixed a bug in the Command Register declaration. rherveille 7836d 20h /.
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7846d 19h /.
31 Core is now a Multimaster I2C controller. rherveille 7850d 20h /.
30 Small code simplifications rherveille 7850d 20h /.
29 Core is now a Multimaster I2C controller rherveille 7850d 21h /.
28 *** empty log message *** rherveille 7876d 14h /.
27 Cleaned up code rherveille 7876d 14h /.
26 *** empty log message *** rherveille 7879d 22h /.
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7907d 18h /.
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7907d 18h /.
23 *** empty log message *** rherveille 8035d 00h /.
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8045d 05h /.
21 no message rherveille 8131d 06h /.
20 Added Appendix A rherveille 8131d 06h /.
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8135d 02h /.

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