OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [.] - Rev 45

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
45 Added slave address configurability rherveille 7506d 12h /.
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7591d 14h /.
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7591d 14h /.
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7601d 12h /.
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7601d 12h /.
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7601d 12h /.
39 Forgot an 'end if' :-/ rherveille 7621d 08h /.
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7624d 16h /.
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7661d 07h /.
36 Fixed cmd_ack generation item (no bug). rherveille 7776d 08h /.
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7809d 23h /.
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7813d 21h /.
33 Fixed a bug in the Command Register declaration. rherveille 7836d 06h /.
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7846d 05h /.
31 Core is now a Multimaster I2C controller. rherveille 7850d 07h /.
30 Small code simplifications rherveille 7850d 07h /.
29 Core is now a Multimaster I2C controller rherveille 7850d 08h /.
28 *** empty log message *** rherveille 7876d 00h /.
27 Cleaned up code rherveille 7876d 00h /.
26 *** empty log message *** rherveille 7879d 08h /.

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.