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49 Added testbench rherveille 7405d 08h /.
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7406d 16h /.
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7415d 12h /.
46 Fixed slave address MSB='1' bug rherveille 7490d 12h /.
45 Added slave address configurability rherveille 7490d 12h /.
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7575d 15h /.
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7575d 15h /.
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7585d 13h /.
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7585d 13h /.
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7585d 13h /.
39 Forgot an 'end if' :-/ rherveille 7605d 09h /.
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7608d 16h /.
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7645d 08h /.
36 Fixed cmd_ack generation item (no bug). rherveille 7760d 09h /.
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7793d 23h /.
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7797d 21h /.
33 Fixed a bug in the Command Register declaration. rherveille 7820d 07h /.
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7830d 06h /.
31 Core is now a Multimaster I2C controller. rherveille 7834d 07h /.
30 Small code simplifications rherveille 7834d 07h /.

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