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Rev Log message Author Age Path
66 Fixed type iscl_oen instead of scl_oen rherveille 5601d 23h /.
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5602d 09h /.
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation		 rherveille 5602d 09h /.
63 Added clock synchronization logic
Fixed slave_wait signal		 rherveille 5602d 09h /.
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits		 rherveille 5602d 23h /.
61 Removed synopsys link; it's not used rherveille 6257d 11h /.
60 Added missing semicolons ';' on endif rherveille 6434d 08h /.
59 fixed short scl high pulse after clock stretch rherveille 6439d 09h /.
58 fixed (n)ack generation rherveille 6471d 11h /.
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6471d 11h /.
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 7024d 08h /.
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7025d 10h /.
54 Fixed scl, sda delay. rherveille 7025d 10h /.
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7321d 08h /.
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7321d 09h /.
51 Fixed simulation issue when writing to CR register rherveille 7375d 09h /.
50 *** empty log message *** rherveille 7390d 04h /.
49 Added testbench rherveille 7390d 04h /.
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7391d 12h /.
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7400d 08h /.

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