OpenCores
URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [.] - Rev 13

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
13 Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v).		 dgisselq 2886d 04h /.
12 A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build.		 dgisselq 2887d 06h /.
11 Files necessary to simulate the entire Arty board--everything at the fastmaster
module and below.		 dgisselq 2887d 06h /.
10 Updated flash data and test files, for a flash that produces it's answers a
clock after I'm expecting them.		 dgisselq 2887d 06h /.
9 Adding copywrite statement (oops). dgisselq 2887d 06h /.
8 Fixes the makefile so it builds a complete testbench suite, emulating the
entire Arty board.		 dgisselq 2887d 06h /.
7 This implements the coordination of a massive build/test suite--just not the
actual configuration file itself.		 dgisselq 2887d 06h /.
6 Minor updates, mostly to support the development of the DDR3 SDRAM--such
as creating addresses for the debugging scope used to figure out what's
going on with it.		 dgisselq 2887d 06h /.
5 Initial checkin, this time of the bench testing s/w. dgisselq 2902d 10h /.
4 Initial host software pack. dgisselq 2902d 10h /.
3 Initial set of files. The flash appears to work, memory hasn't been started,
the MDIO controller works in simulation, etc. Everything below fasttop.v works
at 200MHz (not the CPU---yet).		 dgisselq 2902d 10h /.
2 Initial documentation/proposed specification. (I'm writing the spec as I'm
building the core.)		 dgisselq 2903d 04h /.
1 The project and the structure was created root 2903d 08h /.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.