URL https://opencores.org/ocsvn/single_port/single_port/trunk

Subversion Repositories single_port

[/] [.] - Rev 14

Rev	Log message	Author	Age	Path
14	Address is only converted to integer when chip enable is active in order to avoid simulator warnings	mgeng	6175d 16h	/.
13	rnw replaced by nce, nwe and noe, tristate drivers added	mgeng	6903d 14h	/.
12	rnw replaced by nce, nwe and noe, replaces timing.jpg	mgeng	6903d 14h	/.
11	replaced by timing.png	mgeng	6903d 14h	/.
10	rnw replaced by nce, nwe and noe, replaces tbschematic.jpg	mgeng	6903d 14h	/.
9	replaced by tbschematic.png	mgeng	6903d 14h	/.
8	Constant PAGEDEPTH moved from single_port_pkg to linked_list_mem_pkg because it's only used in the linked list implementation	mgeng	6917d 18h	/.
7	PAGENUM constant removed because the address bus width provides this information	mgeng	6928d 10h	/.
6	Buses unconstrained, LGPL header added	mgeng	6941d 09h	/.
5	Version 2.1 from February 1999	mgeng	6941d 09h	/.
4	Buses unconstrained, triggered not only with rnw but also with address and data bus transactions	mgeng	6941d 09h	/.
3	This commit was manufactured by cvs2svn to create tag 'REL'.		7943d 07h	/.
2	initial checkin	rpaley_yid	7943d 07h	/.
1	Standard project directories initialized by cvs2svn.		7943d 07h	/.