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Rev Log message Author Age Path
164 initial check-in arniml 7074d 20h /.
163 add bug
Wrong clock applied to T0
arniml 7075d 19h /.
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i
arniml 7075d 19h /.
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7107d 00h /.
160 add others to case statement arniml 7227d 20h /.
159 fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 arniml 7227d 20h /.
158 added hierarchies t8039_notri and t8048_notri arniml 7227d 20h /.
157 removed obsolete constant arniml 7227d 20h /.
156 added hierarchy t8039_notri arniml 7227d 20h /.
155 initial check-in arniml 7227d 20h /.
154 added t8039_notri hierarchy arniml 7227d 20h /.
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus
arniml 7228d 18h /.
152 added hierarchy t8048_notri and system components package arniml 7229d 08h /.
151 added hierarchy t8048_notri and components package for t48 systems arniml 7229d 08h /.
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled
arniml 7229d 16h /.
149 update arniml 7229d 17h /.
148 initial check-in arniml 7229d 17h /.
147 initial check-in for release 0.5 BETA arniml 7265d 18h /.
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
arniml 7266d 18h /.
145 remove PROG and end of XTAL2, see comment for details arniml 7266d 19h /.

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