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Rev Log message Author Age Path
170 intermediate update arniml 7038d 08h /.
169 initial check-in arniml 7038d 14h /.
168 change address range of wb_master arniml 7038d 14h /.
167 simplify address range:
- configuration range
- Wishbone range
arniml 7038d 14h /.
166 assign default for state_s arniml 7040d 05h /.
165 add component wb_master.vhd arniml 7041d 04h /.
164 initial check-in arniml 7041d 04h /.
163 add bug
Wrong clock applied to T0
arniml 7042d 04h /.
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i
arniml 7042d 04h /.
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7073d 08h /.
160 add others to case statement arniml 7194d 04h /.
159 fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 arniml 7194d 04h /.
158 added hierarchies t8039_notri and t8048_notri arniml 7194d 04h /.
157 removed obsolete constant arniml 7194d 05h /.
156 added hierarchy t8039_notri arniml 7194d 05h /.
155 initial check-in arniml 7194d 05h /.
154 added t8039_notri hierarchy arniml 7194d 05h /.
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus
arniml 7195d 02h /.
152 added hierarchy t8048_notri and system components package arniml 7195d 17h /.
151 added hierarchy t8048_notri and components package for t48 systems arniml 7195d 17h /.

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