URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [.] - Rev 184

Rev	Log message	Author	Age	Path
184	initial check-in	arniml	6886d 13h	/.
183	fix missing assignment to outclock	arniml	6886d 16h	/.
182	intermediate version	arniml	6966d 14h	/.
181	fix typo	arniml	6966d 17h	/.
180	introduce prefix 't48_' for wb_master entity and configuration	arniml	6974d 23h	/.
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	6974d 23h	/.
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	6976d 11h	/.
177	Implement db_dir_o glitch-safe	arniml	6976d 11h	/.
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	6976d 11h	/.
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	6977d 14h	/.
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	6977d 14h	/.
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	6977d 14h	/.
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7006d 11h	/.
171	remove obsolete output stack_high_o	arniml	7007d 11h	/.
170	intermediate update	arniml	7008d 17h	/.
169	initial check-in	arniml	7008d 23h	/.
168	change address range of wb_master	arniml	7008d 23h	/.
167	simplify address range: - configuration range - Wishbone range	arniml	7008d 23h	/.
166	assign default for state_s	arniml	7010d 14h	/.
165	add component wb_master.vhd	arniml	7011d 14h	/.