OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [.] - Rev 226

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
226 replaced syn_ram with generic_ram_ena arniml 6599d 18h /.
225 replaced syn_rom and syn_ram with t48_rom and generic_ram_ena arniml 6599d 18h /.
224 initial check-in arniml 6599d 18h /.
223 obsoleted arniml 6599d 18h /.
222 add note about clock enable for data memory RAM macro arniml 6600d 18h /.
221 new input xtal_en_i arniml 6600d 18h /.
220 new input xtal_en_i arniml 6600d 18h /.
219 new input xtal_en_i gates xtal_i base clock arniml 6600d 18h /.
218 simplifications arniml 6687d 02h /.
217 update for release 0.6.1 beta arniml 6755d 22h /.
216 assign clk_i to outclock arniml 6817d 22h /.
215 suppress p2_output_pch_o when MOVX operation is accessing the
external memory		 arniml 6817d 22h /.
214 fix sensitivity list arniml 6825d 00h /.
213 properly drive P1 and P2 with low impedance markers arniml 6829d 19h /.
212 add bug reports
"Problem when INT and JMP"
"P2 Port value restored after expander access"		 arniml 6829d 22h /.
211 wire signals for P2 low impedance marker issue arniml 6830d 21h /.
210 entity changes for P2 low impedance marker issue arniml 6830d 21h /.
209 entity changes for P2 low impedance issue arniml 6830d 21h /.
208 wire signals for P2 low impeddance marker issue arniml 6830d 21h /.
207 entity changes for P2 low impedance trigger issue arniml 6830d 22h /.

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.