URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [.] - Rev 264

Rev	Log message	Author	Age	Path
264	Final synthesis results. Gates, sdc, tcl, conf, etc.	creep	5415d 12h	/.
263	Added the final reports from synthesis without a VCD	creep	5415d 13h	/.
262	Final synthesis script.	creep	5415d 13h	/.
261	Added a better clock gating scheme with enable sharing	creep	5415d 15h	/.
260	removing useless files	creep	5418d 10h	/.
259	sync	creep	5418d 10h	/.
258	Fixed the input parametric testing logic, removed a pad.	creep	5418d 10h	/.
257	Modified script for DFT	creep	5440d 13h	/.
256	fp files	creep	5440d 13h	/.
255	Changed the PADS verilog description to minimize violations	creep	5440d 13h	/.
254	Fixed a latch in the design	creep	5440d 13h	/.
253	Changed the rw_mem signal name in the hierarchy	creep	5463d 13h	/.
252	Added a stubs file for the pads.	creep	5463d 14h	/.
251	Added the io wrapper	creep	5463d 16h	/.
250	Synthesis script changed	creep	5463d 17h	/.
249	Renamed the synthesis script	creep	5464d 13h	/.
248	Added a low power synthesis script	creep	5469d 11h	/.
247	Added the cpu mapped verilog	creep	5469d 11h	/.
246	Added some older files plus the first syn script	creep	5470d 16h	/.
245	Added a few dirs for the synthesis	creep	5470d 16h	/.