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Rev Log message Author Age Path
17 New directory structure. root 5577d 19h /.
16 UART16750: Added example project hasw 5598d 06h /.
15 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5607d 09h /.
14 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5608d 11h /.
13 UART16750: Added automatic flow control hasw 5621d 11h /.
12 UART16750: Updated stimuli script with automatic flow control tests hasw 5621d 11h /.
11 UART16750: Removed dependency from std_logic_unsigned hasw 5621d 12h /.
10 UART16750: Removed dependency from std_logic_unsigned hasw 5621d 12h /.
9 Registered control line outputs hasw 5630d 13h /.
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5630d 13h /.
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5631d 18h /.
6 THR empty interrupt register connected to RST hasw 5631d 19h /.
5 Removed old component hasw 5632d 13h /.
4 Removed swap file hasw 5632d 14h /.
3 This commit was manufactured by cvs2svn to create tag 'Import'. 5632d 14h /.
2 Imported sources hasw 5632d 14h /.
1 Standard project directories initialized by cvs2svn. 5632d 14h /.

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