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64 Added old uploaded documents to new repository. root 5724d 17h /.
63 Added old uploaded documents to new repository. root 5724d 23h /.
62 New directory structure. root 5724d 23h /.
61 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7719d 20h /.
60 all WB outputs are registered, but just when we dont use cursors markom 7719d 20h /.
59 Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors. rherveille 7752d 02h /.
58 Enabled Fifo Underrun test rherveille 7752d 02h /.
57 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
2) Changed top level and pixel generator to reflect changes in the fifo.
3) Changed a bug in vga_fifo.
4) Changed pixel generator and wishbone master to reflect changes.		 rherveille 7772d 22h /.
56 Removed 'or negedge arst' from sluint/luint sensitivity list rherveille 7801d 18h /.
55 Initial release. rherveille 7858d 19h /.
54 Added DVI tests rherveille 7858d 19h /.
53 Fixed some Wishbone RevB.3 related bugs.
Changed layout of the core. Blocks are located more logically now.
Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.		 rherveille 7859d 00h /.
52 Numerous updates and added checks rherveille 7859d 00h /.
51 Forgot to change document revision number rherveille 7906d 18h /.
50 Forgot to change document revision rherveille 7906d 18h /.
49 Added WISHBONE revB.3 signals rherveille 7906d 19h /.
48 WISHBONE revB.3 signals added rherveille 7906d 19h /.
47 Added wb_b3_check
Removed ud_cnt, ro_cnt		 rherveille 7907d 16h /.
46 Added WISHBONE revB.3 sanity checks rherveille 7907d 16h /.
45 Changed timing generator; made it smaller and easier. rherveille 7907d 21h /.

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